The Silicon Floor Show: What CES 2026 Told Us About the Next Compute Cycle

CES has a rhythm to it. Every January the industry empties its roadmap onto a Las Vegas stage, the slides get brighter, the multipliers get larger, and by March the reviewers quietly reset the baseline. The trick to reading it is to separate the announcements that move the floor from the ones that just repaint it. This year the floor moved in four places, all on the same Monday, all pointed at the same thing: putting more AI compute at every altitude, from the datacenter rack down to the thin-and-light in your bag.

Worth stating plainly before the specs start flying. Almost every number below is a vendor's own, measured on a vendor's own bench against a comparison the vendor chose. That does not make them false. It makes them the ceiling, not the floor. Where a figure comes from the company's newsroom I have said so; where it leans on the trade press, I have flagged it.

NVIDIA Rubin: the platform, not the card

Jensen Huang did not announce a new GeForce card. He announced a datacenter. NVIDIA formally launched Rubin, named after the astronomer Vera Rubin, and called it the company's first "extreme-codesigned" six-chip platform, now in full production. The six chips are the Vera CPU, the Rubin GPU, the NVLink 6 switch, the ConnectX-9 SuperNIC, the BlueField-4 DPU, and the Spectrum-6 Ethernet switch. You do not buy one of these. You buy the rack.

The headline economics come straight from NVIDIA's own newsroom: up to a 10x reduction in inference token cost and 4x fewer GPUs to train a mixture-of-experts model, both measured against Blackwell. Per-GPU, NVIDIA lists 50 PFLOPS of NVFP4 inference (5x Blackwell GB200) and 35 PFLOPS of NVFP4 training, with the Rubin GPU built from two reticle dies totalling 336 billion transistors and up to 288GB of HBM4 per GPU. Rubin is in full production now; partner availability is H2 2026, with AWS, Google Cloud, Microsoft, and Oracle among the first to deploy.

The thing to hold onto here is the framing. NVIDIA has stopped selling chips and started selling total cost of ownership. When the pitch is "one-tenth the cost per token," the audience is not a gamer, it is a CFO at a hyperscaler weighing a nine-figure buildout. The tell was the venue: NVIDIA held this at the Fontainebleau rather than take a main keynote slot, which is what confidence looks like when you no longer need the stage.

On the gaming side, which got a fraction of the oxygen, NVIDIA announced DLSS 4.5 with Dynamic Multi Frame Generation, a 6X Multi Frame Generation mode, and a second-generation transformer model for Super Resolution. Over 250 games and apps now support DLSS 4. No new RTX silicon. Read that omission for what it is: the consumer card is no longer where the company's attention lives.

Intel Panther Lake: the turnaround's first real exam

If Rubin was a victory lap, Intel Core Ultra Series 3, codenamed Panther Lake, was a sat exam. This is the first high-volume consumer product built on Intel 18A, the process node with RibbonFET gate-all-around transistors and PowerVia backside power delivery, and it is designed and manufactured in the United States. For a company whose foundry story has been mostly promises for three years, shipping a real chip on the real node is the whole point.

The lineup tops out at up to 16 CPU cores, up to 12 Xe3 GPU cores, and up to 50 NPU TOPS, which clears Microsoft's 40-TOPS Copilot+ bar. Intel's own performance footnotes claim up to 60% better multithreaded performance versus Lunar Lake (Cinebench 2024, X9 388H vs 288V at 25W) and up to 77% better gaming (geomean across 45 titles at 1080p with upscaling), plus up to 27 hours of video playback on the flagship. More than 200 partner designs are coming, with preorders from January 6 and broad availability January 27.

Two things matter more than the multipliers. First, Panther Lake collapses Intel's split platform back into one: Series 2 was the efficient-but-TSMC-fabbed Lunar Lake alongside the less-loved Arrow Lake, and Panther Lake unifies them on a single architecture with Intel supplying the compute tile itself. Second, the dependency is not gone. The I/O tile and the larger 12-core GPU tile are still fabbed at TSMC, so "designed and manufactured in the US" applies to the piece that matters most, the 18A compute tile, and not to the whole package. That is progress worth naming honestly rather than overselling.

AMD Ryzen AI 400 and the Instinct stack

AMD used Lisa Su's opening keynote to do what AMD does well lately: cover the whole board. On the client side, the Ryzen AI 400 Series and Ryzen AI PRO 400 Series standardise a 60 TOPS NPU with up to 12 Zen 5 cores and full ROCm support, with systems shipping in Q1 2026. It is worth being honest that this is a refresh built on existing Strix Point and Krackan Point silicon rather than a new architecture, but standardising 60 TOPS across the client stack and bringing Copilot+ to desktop is a real ecosystem move. The Ryzen AI Max+ 392 and 388 push to 128GB unified memory and 128-billion-parameter models locally, and the Ryzen AI Halo developer mini-PC ships in Q2 preloaded with ROCm.

In the datacenter, AMD introduced the Instinct MI440X, an eight-GPU enterprise accelerator, alongside the MI430X for sovereign and HPC work, and previewed the MI500 Series for 2027 with a claimed up-to-1,000x AI performance gain over the 2023-era MI300X. The rack-scale story is Helios: AMD's own event materials put it at up to 2.9 exaflops per rack on MI455X accelerators, a double-wide design weighing nearly 7,000 pounds. That is roughly two compact cars of silicon and copper, which tells you exactly how physical this AI buildout has become.

The MI500's thousand-fold claim is the one to file under "believe it when an independent benchmark says so." A 2027 part compared against a 2023 part across an undefined workload is marketing arithmetic, not a spec.

Qualcomm Snapdragon X2: Arm's second serious swing

The quieter but arguably most consequential launch was Qualcomm's Snapdragon X2 Plus, because it is the generation where Windows-on-Arm stops being an experiment. The X2 Plus comes in 10-core and 6-core SKUs, both boosting to 4 GHz, with an 80 TOPS NPU, up to 128GB of LPDDR5X, and Qualcomm-claimed gains of 35% single-core and 17% multi-core over the prior generation. The flagship X2 Elite Extreme runs 18 cores of third-gen Oryon to 4.7 GHz with 53MB of cache, built on TSMC 3nm.

An 80 TOPS NPU is double Microsoft's Copilot+ threshold, and when the review embargo lifted in April the second-generation Arm parts reportedly outpaced Panther Lake in several benchmarks. That is the real story of this CES for the laptop you actually buy: two credible x86-versus-Arm answers arriving in the same window, both clearing the AI-PC bar with room to spare, which means 2026 is the first year the Windows-on-Arm question is genuinely competitive rather than aspirational.

What actually moved

Strip away the multipliers and the shape is clear. NVIDIA is selling racks and token economics to hyperscalers and has effectively left the CES consumer stage. Intel shipped proof that 18A is real, with an honest asterisk on which tiles are still TSMC's. AMD covered every altitude and leaned hardest on rack-scale physicality. Qualcomm made Arm on Windows a real choice rather than a compromise.

The one number worth carrying into the rest of the year is Rubin's ten-times-cheaper token. If it holds up in production, and NVIDIA's track record says treat it as plausible but unproven, it does not just make existing inference cheaper. It makes workloads that were uneconomical yesterday viable tomorrow, which is how you expand a market rather than just serve it. Everything else on that Monday was a chip. That was a thesis.

Sources: NVIDIA Rubin newsroom, NVIDIA CES blog, Tom's Hardware on Rubin NVFP4 figures, Intel Core Ultra Series 3 newsroom, AMD CES 2026 keynote release, AMD CES event page, Qualcomm Snapdragon X2 Elite. The X2 Elite/Plus specs and the April review-wave comparison against Panther Lake draw on Qualcomm's product page plus trade-press benchmark coverage; treat the head-to-head framing as provisional pending independent testing.